ptos/amd64: cpu: Add interrupt descriptor table
Signed-off-by: Chloe M. <chloe@mensia.org>
This commit is contained in:
@@ -0,0 +1,47 @@
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/*
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* Copyright (c) 2026, Chloe M.
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* Provided under the BSD-3 clause.
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*
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* Description: AMD64 interrupt gate management
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* Author: Chloe M.
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*/
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#include <machine/idt.h>
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#include <machine/gdt.h>
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#include <ptdef.h>
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static IDT_GATE Idt[256];
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ALIGN(8) IDTR Idtr = {
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.Limit = sizeof(Idt) - 1,
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.Offset = (UPTR)&Idt[0]
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};
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VOID
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MdIdtSetGate(UCHAR Vector, UPTR Offset, UCHAR Type, UCHAR Ist)
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{
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IDT_GATE *Gate;
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Gate = &Idt[Vector];
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Gate->OffsetLow16 = Offset & 0xFFFF;
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Gate->OffsetMid16 = (Offset >> 16) & 0xFFFF;
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Gate->OffsetHigh32 = (Offset >> 32) & 0xFFFFFFFF;
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Gate->Reserved = 0;
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Gate->Zero = 0;
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Gate->Zero1 = 0;
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Gate->Type = Type;
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Gate->Dpl = (Type == IDT_USER_GATE) ? 3 : 0;
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Gate->Present = 1;
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Gate->Ist = Ist;
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Gate->SegmentSel = GDT_KCODE;
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}
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VOID
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MdIdtLoad(VOID)
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{
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ASMV(
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"lidt %0"
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:
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: "m" (Idtr)
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: "memory"
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);
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}
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@@ -16,4 +16,51 @@
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#define IDT_TRAP_GATE 0x8F
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#define IDT_USER_GATE 0xEE
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/*
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* Represents an interupt gate descriptor
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*
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* Refer to section 6.14.1 of the Intel SDM
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*/
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typedef struct {
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USHORT OffsetLow16;
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USHORT SegmentSel;
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UCHAR Ist : 3;
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UCHAR Zero : 5;
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UCHAR Type : 4;
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UCHAR Zero1 : 1;
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UCHAR Dpl : 2;
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UCHAR Present : 1;
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USHORT OffsetMid16;
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ULONG OffsetHigh32;
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ULONG Reserved;
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} IDT_GATE;
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/*
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* Refers to the base and limit of the interrupt
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* descriptor table.
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*
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* Refer to section 6.10 of the Intel SDM
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*/
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typedef struct PACKED {
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USHORT Limit;
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UQUAD Offset;
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} IDTR;
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/*
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* Set an interrupt descriptor table gate
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*
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* @Vector: Interrupt vector to set
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* @Offset: Offset of interrupt service routine
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* @Type: Interrupt gate type
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* @Ist: Interrupt stack table index
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*/
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VOID MdIdtSetGate(UCHAR Vector, UPTR Offset, UCHAR Type, UCHAR Ist);
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/*
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* Load the interrupt descriptor table
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*
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* XXX: This must be called once per processor
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*/
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VOID MdIdtLoad(VOID);
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#endif /* !_MACHINE_IDT_H_ */
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