7a2aec4e12
Signed-off-by: Chloe M <chloe@mensia.org>
54 lines
1023 B
C
54 lines
1023 B
C
/*
|
|
* Copyright (c) 2026, Chloe M.
|
|
* Provided under the BSD-3 clause.
|
|
*
|
|
* Description: Kernel processor control region
|
|
* Author: Chloe M.
|
|
*/
|
|
|
|
#ifndef _HAL_KPCR_H_
|
|
#define _HAL_KPCR_H_ 1
|
|
|
|
#include <ptdef.h>
|
|
#include <ex/pool.h>
|
|
#include <ke/sched.h>
|
|
#include <machine/mcb.h>
|
|
|
|
/*
|
|
* The kernel processor control region contains MI
|
|
* processor information.
|
|
*
|
|
* @Id: Logical processor ID assigned by us
|
|
* @PoolRegion: Allocator pool region
|
|
* @SchedQueue: Per-core scheduler queue
|
|
* @Mcb: Machine core block
|
|
*/
|
|
typedef struct {
|
|
USHORT Id;
|
|
POOL_REGION PoolRegion;
|
|
SCHED_QUEUE SchedQueue;
|
|
MCB Mcb;
|
|
} KPCR;
|
|
|
|
/*
|
|
* Phase 1 processor initialization
|
|
*
|
|
* @Kpcr: KPCR of processor to initialize
|
|
*/
|
|
VOID HalKpcrP1Init(KPCR *Kpcr);
|
|
|
|
/*
|
|
* Phase 2 processor initialization
|
|
*
|
|
* @Kpcr: KPCR of processor to initialize
|
|
*/
|
|
VOID HalKpcrP2Init(KPCR *Kpcr);
|
|
|
|
/*
|
|
* Obtain the KPCR of the current processor
|
|
* core
|
|
*/
|
|
KPCR *HalKpcrCurrent(VOID);
|
|
|
|
#endif /* !_HAL_KPCR_H_ */
|