32 lines
973 B
C
32 lines
973 B
C
/*
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* Copyright (c) 2026, Chloe M.
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* Provided under the BSD-3 clause.
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*
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* Description: Platform MMU bits
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* Author: Chloe M.
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*/
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#ifndef _MACHINE_MMU_H_
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#define _MACHINE_MMU_H_ 1
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#include <ptdef.h>
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/*
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* Page-Table Entry (PTE) flags
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*
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* See Intel SDM Vol 3A, Section 4.5, Table 4-19
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*/
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#define PTE_ADDR_MASK 0x000FFFFFFFFFF000
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#define PTE_P BIT(0) /* Present */
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#define PTE_RW BIT(1) /* Writable */
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#define PTE_US BIT(2) /* User r/w allowed */
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#define PTE_PWT BIT(3) /* Page-level write-through */
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#define PTE_PCD BIT(4) /* Page-level cache disable */
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#define PTE_ACC BIT(5) /* Accessed */
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#define PTE_DIRTY BIT(6) /* Dirty (written-to page) */
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#define PTE_PS BIT(7) /* Page size */
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#define PTE_GLOBAL BIT(8) /* Global; sticky */
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#define PTE_NX BIT(63) /* Execute-disable */
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#endif /* !_MACHINE_MMU_H_ */
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