98 lines
2.4 KiB
C
98 lines
2.4 KiB
C
/*
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* Copyright (c) 2026, Chloe M.
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* Provided under the BSD-3 clause.
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*
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* Description: Kernel processor control region
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* Author: Chloe M.
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*/
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#include <hal/kpcr.h>
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#include <ke/bugcheck.h>
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#include <machine/idt.h>
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#include <machine/trap.h>
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#include <machine/msr.h>
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#include <machine/lapic.h>
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#include <machine/gdt.h>
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/* Externs */
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extern GDT_ENTRY g_GDT[GDT_ENTRY_COUNT];
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/*
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* Initialize interrupts for the current processor
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*/
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static VOID
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InitInterrupts(VOID)
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{
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MdIdtSetGate(0x00, (UPTR)TrapDivError, IDT_TRAP_GATE, 0);
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MdIdtSetGate(0x01, (UPTR)TrapDebugException, IDT_TRAP_GATE, 0);
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MdIdtSetGate(0x02, (UPTR)TrapNmi, IDT_TRAP_GATE, 0);
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MdIdtSetGate(0x03, (UPTR)TrapBreakPoint, IDT_TRAP_GATE, 0);
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MdIdtSetGate(0x04, (UPTR)TrapOverflow, IDT_TRAP_GATE, 0);
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MdIdtSetGate(0x05, (UPTR)TrapBoundRange, IDT_TRAP_GATE, 0);
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MdIdtSetGate(0x06, (UPTR)TrapInvalidOpcode, IDT_TRAP_GATE, 0);
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MdIdtSetGate(0x07, (UPTR)TrapNoCoprocessor, IDT_TRAP_GATE, 0);
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MdIdtSetGate(0x08, (UPTR)TrapDoubleFault, IDT_TRAP_GATE, 0);
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MdIdtSetGate(0x09, (UPTR)TrapReserved, IDT_TRAP_GATE, 0);
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MdIdtSetGate(0x0A, (UPTR)TrapInvalidTss, IDT_TRAP_GATE, 0);
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MdIdtSetGate(0x0B, (UPTR)TrapSegNotPresent, IDT_TRAP_GATE, 0);
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MdIdtSetGate(0x0C, (UPTR)TrapStackSegmentFault, IDT_TRAP_GATE, 0);
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MdIdtSetGate(0x0D, (UPTR)TrapGeneralProtection, IDT_TRAP_GATE, 0);
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MdIdtSetGate(0x0E, (UPTR)TrapPageFault, IDT_TRAP_GATE, 0);
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MdIdtLoad();
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}
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KPCR *
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HalKpcrCurrent(VOID)
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{
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KPCR *Kpcr;
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Kpcr = (KPCR *)MdRdmsr(IA32_GS_BASE);
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if (Kpcr == NULL) {
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KeBugCheck(
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BUGCHECK_UNBOUND_RESRC,
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"KPCR not bound in IA32_GS_BASE\n"
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);
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}
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return Kpcr;
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}
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VOID
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HalKpcrP1Init(KPCR *Kpcr)
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{
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/* Initialize interrupts for this core */
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InitInterrupts();
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/* Save the current KPCR */
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MdWrmsr(IA32_GS_BASE, (UPTR)Kpcr);
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}
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VOID
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HalKpcrP2Init(KPCR *Kpcr)
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{
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TSS_DESCRIPTOR *TssDesc;
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/* Initialize per-processor pools */
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ExPoolRegionInit(&Kpcr->PoolRegion);
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/* Initialize the Local APIC unit */
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MdLapicInit(Kpcr);
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/* Load the Task State Segment */
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TssDesc = (TSS_DESCRIPTOR *)&g_GDT[GDT_TSS_INDEX];
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MdTssInit(TssDesc);
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ASMV(
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"mov %0, %%ax\n"
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"ltr %%ax\n"
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:
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: "i" (GDT_TSS)
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: "memory"
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);
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/* Initialize the scheduler queue */
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SCHED_QUEUE_INIT(&Kpcr->SchedQueue);
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/* Enable interrupts */
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ASMV("sti");
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}
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