From cf7a1b88b2d63718c4de0e6eaaf357c4dbdc5470 Mon Sep 17 00:00:00 2001 From: Chloe M Date: Fri, 10 Jul 2026 20:59:56 -0400 Subject: [PATCH] ptos/amd64: mmu: Add MMU related bit defs Signed-off-by: Chloe M --- service/ptos/head/arch/amd64/mmu.h | 31 ++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 service/ptos/head/arch/amd64/mmu.h diff --git a/service/ptos/head/arch/amd64/mmu.h b/service/ptos/head/arch/amd64/mmu.h new file mode 100644 index 0000000..0179e11 --- /dev/null +++ b/service/ptos/head/arch/amd64/mmu.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2026, Chloe M. + * Provided under the BSD-3 clause. + * + * Description: Platform MMU bits + * Author: Chloe M. + */ + +#ifndef _MACHINE_MMU_H_ +#define _MACHINE_MMU_H_ 1 + +#include + +/* + * Page-Table Entry (PTE) flags + * + * See Intel SDM Vol 3A, Section 4.5, Table 4-19 + */ +#define PTE_ADDR_MASK 0x000FFFFFFFFFF000 +#define PTE_P BIT(0) /* Present */ +#define PTE_RW BIT(1) /* Writable */ +#define PTE_US BIT(2) /* User r/w allowed */ +#define PTE_PWT BIT(3) /* Page-level write-through */ +#define PTE_PCD BIT(4) /* Page-level cache disable */ +#define PTE_ACC BIT(5) /* Accessed */ +#define PTE_DIRTY BIT(6) /* Dirty (written-to page) */ +#define PTE_PS BIT(7) /* Page size */ +#define PTE_GLOBAL BIT(8) /* Global; sticky */ +#define PTE_NX BIT(63) /* Execute-disable */ + +#endif /* !_MACHINE_MMU_H_ */