ptos/amd64: cpu: Add high-level interrupt registration

Signed-off-by: Chloe M <chloe@mensia.org>

service/ptos/head/arch/amd64/intr.h

@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2026, Chloe M.
+ * Provided under the BSD-3 clause.
+ *
+ * Description: High-level interrupt management
+ * Author:      Chloe M.
+ */
+
+#ifndef _MACHINE_INTR_H_
+#define _MACHINE_INTR_H_ 1
+
+/* Interrupt priority class shift operand */
+#define IPRI_CLASS_SHIFT 4
+
+#endif  /* !_MACHINE_INTR_H_ */

service/ptos/head/hal/intr.h

@@ -10,6 +10,7 @@
 #define _HAL_INTR_H_ 1
 
 #include <ptdef.h>
+#include <ptapi/status.h>
 
 /*
  * Represents value interrupt request levels that can be set within
@@ -40,4 +41,15 @@ typedef struct _INTR_HANDLER {
     BOOLEAN Present;
 } INTR_HANDLER;
 
+/*
+ * Register an interrupt handler and obtain the interrupt
+ * vector.
+ *
+ * @Handler:  Handler to register
+ * @IsUser:   If set, is user-level interrupt
+ *
+ * Returned values of zero are invalid
+ */
+UCHAR HalIntrRegister(INTR_HANDLER *Handler, BOOLEAN IsUser);
+
 #endif  /* !_HAL_INTR_H_ */