ptos/amd64+hal: Add interrupt handling + P1 KPCR init

Signed-off-by: Chloe M. <chloe@mensia.org>

service/ptos/arch/amd64/cpu/init.c

@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2026, Chloe M.
+ * Provided under the BSD-3 clause.
+ *
+ * Description: Kernel processor control region
+ * Author:      Chloe M.
+ */
+
+#include <hal/kpcr.h>
+#include <machine/idt.h>
+#include <machine/trap.h>
+
+/*
+ * Initialize interrupts for the current processor
+ */
+static VOID
+InitInterrupts(VOID)
+{
+    MdIdtSetGate(0x00, (UPTR)TrapDivError, IDT_TRAP_GATE, 0);
+    MdIdtSetGate(0x01, (UPTR)TrapDebugException, IDT_TRAP_GATE, 0);
+    MdIdtSetGate(0x02, (UPTR)TrapNmi, IDT_TRAP_GATE, 0);
+    MdIdtSetGate(0x03, (UPTR)TrapBreakPoint, IDT_TRAP_GATE, 0);
+    MdIdtSetGate(0x04, (UPTR)TrapOverflow, IDT_TRAP_GATE, 0);
+    MdIdtSetGate(0x05, (UPTR)TrapBoundRange, IDT_TRAP_GATE, 0);
+    MdIdtSetGate(0x06, (UPTR)TrapInvalidOpcode, IDT_TRAP_GATE, 0);
+    MdIdtSetGate(0x07, (UPTR)TrapNoCoprocessor, IDT_TRAP_GATE, 0);
+    MdIdtSetGate(0x08, (UPTR)TrapDoubleFault, IDT_TRAP_GATE, 0);
+    MdIdtSetGate(0x09, (UPTR)TrapReserved, IDT_TRAP_GATE, 0);
+    MdIdtSetGate(0x0A, (UPTR)TrapInvalidTss, IDT_TRAP_GATE, 0);
+    MdIdtSetGate(0x0B, (UPTR)TrapSegNotPresent, IDT_TRAP_GATE, 0);
+    MdIdtSetGate(0x0C, (UPTR)TrapStackSegmentFault, IDT_TRAP_GATE, 0);
+    MdIdtSetGate(0x0D, (UPTR)TrapGeneralProtection, IDT_TRAP_GATE, 0);
+    MdIdtSetGate(0x0E, (UPTR)TrapPageFault, IDT_TRAP_GATE, 0);
+    MdIdtLoad();
+}
+
+VOID
+HalKpcrP1Init(KPCR *Kpcr)
+{
+    InitInterrupts();
+}

service/ptos/arch/amd64/cpu/trap.c

@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2026, Chloe M.
+ * Provided under the BSD-3 clause.
+ *
+ * Description: Trap dispatch
+ * Author:      Chloe M.
+ */
+
+#include <machine/trap.h>
+#include <ke/bugcheck.h>
+#include <ptdef.h>
+
+#define TRAP_STR(TYPE)              \
+    ((TYPE) >= NELEM(TrapTab))      \
+        ? "bad trap type"           \
+        : TrapTab[(TYPE)]
+
+static const CHAR *TrapTab[] = {
+    [TRAP_DIVERR] = "divide error",
+    [TRAP_DEBUG_EXCEPTION] = "debug exception",
+    [TRAP_NMI] = "non-maskable interrupt",
+    [TRAP_BREAKPOINT] = "breakpoint",
+    [TRAP_OVERFLOW] = "overflow",
+    [TRAP_BOUND_RANGE] = "bound range exceeded",
+    [TRAP_INVALID_OPCODE] = "invalid opcode",
+    [TRAP_NO_COPROCESSOR] = "no math coprocessor",
+    [TRAP_DOUBLE_FAULT] = "double fault",
+    [TRAP_RESERVED] = "reserved exception",
+    [TRAP_INVALID_TSS] = "invalid tss",
+    [TRAP_SEG_NOT_PRESENT] = "segment not present",
+    [TRAP_STACK_SEG_FAULT] = "stack segment fault",
+    [TRAP_GENERAL_PROTECTION] = "general protection fault",
+    [TRAP_PAGE_FAULT] = "page fault"
+};
+
+VOID
+MdTrapDispatch(TRAP_FRAME *TrapFrame)
+{
+    /* Sanity check */
+    if (TrapFrame == NULL) {
+        KeBugCheck(
+            BUGCHECK_UNBOUND_RESRC,
+            "unbound trapframe during dispatch\n"
+        );
+    }
+
+    KeBugCheck(
+        BUGCHECK_EXCEPTION,
+        "got fatal %s\n", TRAP_STR(TrapFrame->Vector)
+    );
+}

service/ptos/arch/amd64/cpu/vector.S

@@ -0,0 +1,145 @@
+/*
+ * Copyright (c) 2026, Chloe M.
+ * Provided under the BSD-3 clause.
+ *
+ * Description: AMD64 interrupt vectors
+ * Author:      Chloe M.
+ */
+
+#include <machine/frameasm.h>
+
+    .text
+    .globl TrapDivError
+TrapDivError:
+    INTR_ENTRY($0x00)
+    mov %rsp, %rdi
+    call MdTrapDispatch
+1:  cli
+    hlt
+    jmp 1b
+
+    .globl TrapDebugException
+TrapDebugException:
+    INTR_ENTRY($0x01)
+    mov %rsp, %rdi
+    call MdTrapDispatch
+1:  cli
+    hlt
+    jmp 1b
+
+    .globl TrapNmi
+TrapNmi:
+    INTR_ENTRY($0x02)
+    mov %rsp, %rdi
+    call MdTrapDispatch
+1:  cli
+    hlt
+    jmp 1b
+
+    .globl TrapBreakPoint
+TrapBreakPoint:
+    INTR_ENTRY($0x03)
+    mov %rsp, %rdi
+    call MdTrapDispatch
+1:  cli
+    hlt
+    jmp 1b
+
+    .globl TrapOverflow
+TrapOverflow:
+    INTR_ENTRY($0x04)
+    mov %rsp, %rdi
+    call MdTrapDispatch
+1:  cli
+    hlt
+    jmp 1b
+
+    .globl TrapBoundRange
+TrapBoundRange:
+    INTR_ENTRY($0x05)
+    mov %rsp, %rdi
+    call MdTrapDispatch
+1:  cli
+    hlt
+    jmp 1b
+
+    .globl TrapInvalidOpcode
+TrapInvalidOpcode:
+    INTR_ENTRY($0x06)
+    mov %rsp, %rdi
+    call MdTrapDispatch
+1:  cli
+    hlt
+    jmp 1b
+
+    .globl TrapNoCoprocessor
+TrapNoCoprocessor:
+    INTR_ENTRY($0x07)
+    mov %rsp, %rdi
+    call MdTrapDispatch
+1:  cli
+    hlt
+    jmp 1b
+
+    .globl TrapDoubleFault
+TrapDoubleFault:
+    INTR_ENTRY_EC($0x08)
+    mov %rsp, %rdi
+    call MdTrapDispatch
+1:  cli
+    hlt
+    jmp 1b
+
+    .globl TrapReserved
+TrapReserved:
+    INTR_ENTRY($0x09)
+    mov %rsp, %rdi
+    call MdTrapDispatch
+1:  cli
+    hlt
+    jmp 1b
+
+    .globl TrapInvalidTss
+TrapInvalidTss:
+    INTR_ENTRY_EC($0x0A)
+    mov %rsp, %rdi
+    call MdTrapDispatch
+1:  cli
+    hlt
+    jmp 1b
+
+    .globl TrapSegNotPresent
+TrapSegNotPresent:
+    INTR_ENTRY_EC($0x0B)
+    mov %rsp, %rdi
+    call MdTrapDispatch
+1:  cli
+    hlt
+    jmp 1b
+
+    .globl TrapStackSegmentFault
+TrapStackSegmentFault:
+    INTR_ENTRY_EC($0x0C)
+    mov %rsp, %rdi
+    call MdTrapDispatch
+1:  cli
+    hlt
+    jmp 1b
+
+    .globl TrapGeneralProtection
+TrapGeneralProtection:
+    INTR_ENTRY_EC($0x0D)
+    mov %rsp, %rdi
+    call MdTrapDispatch
+1:  cli
+    hlt
+    jmp 1b
+
+    .globl TrapPageFault
+TrapPageFault:
+    INTR_ENTRY_EC($0x0E)
+    mov %rsp, %rdi
+    call MdTrapDispatch
+1:  cli
+    hlt
+    jmp 1b

service/ptos/head/arch/amd64/frameasm.h

@@ -29,7 +29,7 @@
     push %rcx               ;\
     push %rbx               ;\
     push %rax               ;\
-    push $VEC
+    push VEC
 
 /*
  * Pop an interrupt vector alongside all general purpose
@@ -60,7 +60,7 @@
  */
 #define INTR_ENTRY_EC(VEC)   \
     cld                     ;\
-    _TRAP_PUSHALL()         ;\
+    _TRAP_PUSHALL(VEC)      ;\
     testb $3, 16(%rsp)      ;\
     jz 1f                   ;\
     lfence                  ;\
@@ -74,7 +74,7 @@
 #define INTR_ENTRY(VEC)     ;\
     cld                     ;\
     push $0                 ;\
-    _TRAP_PUSHALL()         ;\
+    _TRAP_PUSHALL(VEC)      ;\
     testb $3, 8(%rsp)       ;\
     jz 1f                   ;\
     lfence                  ;\

service/ptos/head/arch/amd64/trap.h

@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2026, Chloe M.
+ * Provided under the BSD-3 clause.
+ *
+ * Description: Trap handlers
+ * Author:      Chloe M.
+ */
+
+#ifndef _MACHINE_TRAP_H_
+#define _MACHINE_TRAP_H_ 1
+
+#include <ptdef.h>
+#include <machine/frame.h>
+
+/* Trap vectors */
+#define TRAP_DIVERR             0x00
+#define TRAP_DEBUG_EXCEPTION    0x01
+#define TRAP_NMI                0x02
+#define TRAP_BREAKPOINT         0x03
+#define TRAP_OVERFLOW           0x04
+#define TRAP_BOUND_RANGE        0x05
+#define TRAP_INVALID_OPCODE     0x06
+#define TRAP_NO_COPROCESSOR     0x07
+#define TRAP_DOUBLE_FAULT       0x08
+#define TRAP_RESERVED           0x09
+#define TRAP_INVALID_TSS        0x0A
+#define TRAP_SEG_NOT_PRESENT    0x0B
+#define TRAP_STACK_SEG_FAULT    0x0C
+#define TRAP_GENERAL_PROTECTION 0x0D
+#define TRAP_PAGE_FAULT         0x0E
+
+/* Prototypes of trap functions */
+VOID TrapDivError(VOID);
+VOID TrapDebugException(VOID);
+VOID TrapNmi(VOID);
+VOID TrapBreakPoint(VOID);
+VOID TrapOverflow(VOID);
+VOID TrapBoundRange(VOID);
+VOID TrapInvalidOpcode(VOID);
+VOID TrapNoCoprocessor(VOID);
+VOID TrapDoubleFault(VOID);
+VOID TrapReserved(VOID);
+VOID TrapInvalidTss(VOID);
+VOID TrapSegNotPresent(VOID);
+VOID TrapStackSegmentFault(VOID);
+VOID TrapGeneralProtection(VOID);
+VOID TrapPageFault(VOID);
+VOID TrapLegacySyscall(VOID);
+
+/*
+ * Used to dispatch traps that happen on the processor
+ *
+ * @TrapFrame: Trap frame associated with event
+ */
+VOID MdTrapDispatch(TRAP_FRAME *TrapFrame);
+
+#endif  /* !_MACHINE_TRAP_H_ */

service/ptos/head/hal/kpcr.h

@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2026, Chloe M.
+ * Provided under the BSD-3 clause.
+ *
+ * Description: Kernel processor control region
+ * Author:      Chloe M.
+ */
+
+#ifndef _HAL_KPCR_H_
+#define _HAL_KPCR_H_ 1
+
+#include <ptdef.h>
+
+/*
+ * The kernel processor control region contains MI
+ * processor information.
+ *
+ * @Id:  Logical processor ID assigned by us
+ */
+typedef struct {
+    USHORT Id;
+} KPCR;
+
+/*
+ * Phase 1 processor initialization
+ *
+ * @Kpcr: KPCR of processor to initialize
+ */
+VOID HalKpcrP1Init(KPCR *Kpcr);
+
+#endif  /* !_HAL_KPCR_H_ */

service/ptos/ke/init.c

@@ -11,9 +11,13 @@
 #include <ex/trace.h>
 #include <mm/pm.h>
 #include <hal/serial.h>
+#include <hal/kpcr.h>
 #include <drivers/bootvid/fbio.h>
 #include <string.h>
 
+/* Globals */
+static KPCR BootstrapCore;
+
 /*
  * Display the copyright for legal reasons
  */
@@ -48,4 +52,7 @@ KiKernelInit(VOID)
 
     /* Initialize physical memory */
     MmPmInit();
+
+    /* Phase 1 init of bootstrap core */
+    HalKpcrP1Init(&BootstrapCore);
 }