ptos/amd64+hal: Add interrupt handling + P1 KPCR init

Signed-off-by: Chloe M. <chloe@mensia.org>

service/ptos/head/arch/amd64/frameasm.h

@@ -29,7 +29,7 @@
     push %rcx               ;\
     push %rbx               ;\
     push %rax               ;\
-    push $VEC
+    push VEC
 
 /*
  * Pop an interrupt vector alongside all general purpose
@@ -60,7 +60,7 @@
  */
 #define INTR_ENTRY_EC(VEC)   \
     cld                     ;\
-    _TRAP_PUSHALL()         ;\
+    _TRAP_PUSHALL(VEC)      ;\
     testb $3, 16(%rsp)      ;\
     jz 1f                   ;\
     lfence                  ;\
@@ -74,7 +74,7 @@
 #define INTR_ENTRY(VEC)     ;\
     cld                     ;\
     push $0                 ;\
-    _TRAP_PUSHALL()         ;\
+    _TRAP_PUSHALL(VEC)      ;\
     testb $3, 8(%rsp)       ;\
     jz 1f                   ;\
     lfence                  ;\

service/ptos/head/arch/amd64/trap.h

@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2026, Chloe M.
+ * Provided under the BSD-3 clause.
+ *
+ * Description: Trap handlers
+ * Author:      Chloe M.
+ */
+
+#ifndef _MACHINE_TRAP_H_
+#define _MACHINE_TRAP_H_ 1
+
+#include <ptdef.h>
+#include <machine/frame.h>
+
+/* Trap vectors */
+#define TRAP_DIVERR             0x00
+#define TRAP_DEBUG_EXCEPTION    0x01
+#define TRAP_NMI                0x02
+#define TRAP_BREAKPOINT         0x03
+#define TRAP_OVERFLOW           0x04
+#define TRAP_BOUND_RANGE        0x05
+#define TRAP_INVALID_OPCODE     0x06
+#define TRAP_NO_COPROCESSOR     0x07
+#define TRAP_DOUBLE_FAULT       0x08
+#define TRAP_RESERVED           0x09
+#define TRAP_INVALID_TSS        0x0A
+#define TRAP_SEG_NOT_PRESENT    0x0B
+#define TRAP_STACK_SEG_FAULT    0x0C
+#define TRAP_GENERAL_PROTECTION 0x0D
+#define TRAP_PAGE_FAULT         0x0E
+
+/* Prototypes of trap functions */
+VOID TrapDivError(VOID);
+VOID TrapDebugException(VOID);
+VOID TrapNmi(VOID);
+VOID TrapBreakPoint(VOID);
+VOID TrapOverflow(VOID);
+VOID TrapBoundRange(VOID);
+VOID TrapInvalidOpcode(VOID);
+VOID TrapNoCoprocessor(VOID);
+VOID TrapDoubleFault(VOID);
+VOID TrapReserved(VOID);
+VOID TrapInvalidTss(VOID);
+VOID TrapSegNotPresent(VOID);
+VOID TrapStackSegmentFault(VOID);
+VOID TrapGeneralProtection(VOID);
+VOID TrapPageFault(VOID);
+VOID TrapLegacySyscall(VOID);
+
+/*
+ * Used to dispatch traps that happen on the processor
+ *
+ * @TrapFrame: Trap frame associated with event
+ */
+VOID MdTrapDispatch(TRAP_FRAME *TrapFrame);
+
+#endif  /* !_MACHINE_TRAP_H_ */

service/ptos/head/hal/kpcr.h

@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2026, Chloe M.
+ * Provided under the BSD-3 clause.
+ *
+ * Description: Kernel processor control region
+ * Author:      Chloe M.
+ */
+
+#ifndef _HAL_KPCR_H_
+#define _HAL_KPCR_H_ 1
+
+#include <ptdef.h>
+
+/*
+ * The kernel processor control region contains MI
+ * processor information.
+ *
+ * @Id:  Logical processor ID assigned by us
+ */
+typedef struct {
+    USHORT Id;
+} KPCR;
+
+/*
+ * Phase 1 processor initialization
+ *
+ * @Kpcr: KPCR of processor to initialize
+ */
+VOID HalKpcrP1Init(KPCR *Kpcr);
+
+#endif  /* !_HAL_KPCR_H_ */