stos/amd64: cpu: Add LAPIC driver + MCB in KPCR
Signed-off-by: Chloe M <chloe@mensia.org>
This commit is contained in:
@@ -11,6 +11,7 @@
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#include <machine/idt.h>
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#include <machine/trap.h>
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#include <machine/msr.h>
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#include <machine/lapic.h>
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/*
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* Initialize interrupts for the current processor
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@@ -65,5 +66,9 @@ HalKpcrP1Init(KPCR *Kpcr)
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VOID
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HalKpcrP2Init(KPCR *Kpcr)
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{
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/* Initialize per-processor pools */
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ExPoolRegionInit(&Kpcr->PoolRegion);
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/* Initialize the Local APIC unit */
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MdLapicInit(Kpcr);
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}
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@@ -0,0 +1,352 @@
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/*
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* Copyright (c) 2026, Chloe M.
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* Provided under the BSD-3 clause.
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*
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* Description: Local APIC driver
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* Author: Chloe M.
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*/
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#include <machine/lapic.h>
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#include <machine/lapicreg.h>
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#include <machine/msr.h>
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#include <machine/cpuid.h>
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#include <machine/i8254.h>
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#include <machine/idt.h>
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#include <hal/mmio.h>
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#include <hal/prim.h>
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#include <drivers/acpi/tables.h>
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#include <drivers/acpi/acpi.h>
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#include <mm/vm.h>
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#include <ex/trace.h>
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#include <ke/bugcheck.h>
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/* Local APIC timer vector */
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#define LAPIC_TMR_VECTOR 0x81
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/*
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* Trace only on the bootstrap processor but not on any others
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* to avoid log spam...
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*/
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#define DTRACE_BSP(Fmt, ...) do { \
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ULONG ApicBase; \
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\
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ApicBase = MdRdmsr(IA32_APIC_BASE_MSR); \
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if (ISSET(ApicBase, BIT(8))) { \
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TRACE("[ LAPIC ]: " Fmt, ##__VA_ARGS__); \
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} \
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} while (0);
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/* Globals */
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extern VOID LapicTmrIsr(VOID);
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/*
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* Returns true if the Local APIC unit is supported on the
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* current processor.
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*/
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static BOOLEAN
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LapicIsSupported(VOID)
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{
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ULONG Edx, Unused;
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CPUID(1, Unused, Unused, Unused, Edx);
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return ISSET(Edx, BIT(9)) != 0;
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}
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/*
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* Returns true if the CPU can operate its Local APIC unit
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* in the newer x2APIC mode.
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*/
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static BOOLEAN
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LapicHasX2Apic(VOID)
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{
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ULONG Ecx, Unused;
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CPUID(1, Unused, Unused, Ecx, Unused);
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return ISSET(Ecx, BIT(21)) != 0;
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}
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/*
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* Read a Local APIC register
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*
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* @Mcb: Machine core block
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* @Register: Register to read
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*/
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static UQUAD
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LapicRegRead(MCB *Mcb, ULONG Register)
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{
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ULONG *Base;
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UQUAD Value;
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if (!Mcb->HasX2Apic) {
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Base = PTR_OFFSET(Mcb->LapicBase, Register);
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Value = MMIORead32(Base);
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} else {
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Register >>= 4;
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Value = MdRdmsr(x2APIC_MSR_BASE + Register);
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}
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return Value;
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}
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/*
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* Write a value to a Local APIC register space
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*
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* @Mcb: Machine core block
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* @Register: Register to read
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* @Value: Value to write
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*/
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static VOID
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LapicRegWrite(MCB *Mcb, ULONG Register, UQUAD Value)
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{
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ULONG *Base;
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if (!Mcb->HasX2Apic) {
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Base = PTR_OFFSET(Mcb->LapicBase, Register);
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MMIOWrite32(Base, (ULONG)Value);
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} else {
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Register >>= 4;
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MdWrmsr(x2APIC_MSR_BASE + Register, Value);
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}
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}
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/*
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* Enable the Local APIC unit
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*
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* @Mcb: Machine core block
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*/
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static VOID
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LapicEnable(MCB *Mcb)
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{
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UQUAD ApicBase;
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ULONG Svr, Version;
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const CHAR *mode;
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const CHAR *type = "discrete 82489DX";
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/* Hardware enable the Local APIC unit */
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ApicBase = MdRdmsr(IA32_APIC_BASE_MSR);
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ApicBase |= LAPIC_HW_ENABLE;
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ApicBase |= Mcb->HasX2Apic << x2APIC_ENABLE_SHIFT;
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MdWrmsr(IA32_APIC_BASE_MSR, ApicBase);
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/* Software enable the Local APIC unit */
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Svr = LapicRegRead(Mcb, LAPIC_SVR);
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Svr |= LAPIC_SW_ENABLE;
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LapicRegWrite(Mcb, LAPIC_SVR, Svr);
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/* Check the type */
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Version = LapicRegRead(Mcb, LAPIC_VERSION);
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if ((Version & 0xFF) > 0) {
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type = "integrated";
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}
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mode = Mcb->HasX2Apic ? "x2apic" : "xapic";
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DTRACE_BSP("enabled %s %s\n", type, mode);
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}
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/*
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* Stop the Local APIC timer
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*
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* @Mcb: Machine core block
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*/
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static VOID
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LapicTimerStop(MCB *Mcb)
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{
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if (Mcb == NULL) {
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return;
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}
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LapicRegWrite(Mcb, LAPIC_LVT_TMR, LAPIC_LVT_MASK);
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LapicRegWrite(Mcb, LAPIC_INIT_CNT, 0);
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}
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/*
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* Start the Local APIC timer
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*
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* @Mcb: Machine core block
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* @Mask: True to mask the timer
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* @Mode: Timer mode
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* @Count: Timer count
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*/
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static VOID
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LapicTimerStart(MCB *Mcb, BOOLEAN Mask, UCHAR Mode, ULONG Count)
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{
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ULONG Tmp;
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Tmp = (Mode << 17) | (Mask << 16) | LAPIC_TMR_VECTOR;
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LapicRegWrite(Mcb, LAPIC_LVT_TMR, Tmp);
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LapicRegWrite(Mcb, LAPIC_DCR, 0);
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LapicRegWrite(Mcb, LAPIC_INIT_CNT, Count);
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}
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/*
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* Start the Local APIC timer in oneshot mode
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*
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* @Mcb: Machine core block
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* @Mask: True to mask the timer
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* @Count: Initial count
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*/
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static void
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LapicTimerOneShot(MCB *Mcb, BOOLEAN Mask, ULONG Count)
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{
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LapicTimerStart(Mcb, Mask, LVT_TMR_ONESHOT, Count);
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}
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/*
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* Calibrate the Local APIC timer
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*
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* @Mcb: Machine core block
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*/
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static VOID
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LapicTimerCalibrate(MCB *Mcb)
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{
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const USHORT MAX_SAMPLES = 0xFFFF;
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USHORT TicksStart, TicksEnd;
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USIZE Freq, TicksTotal;
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if (Mcb == NULL) {
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return;
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}
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LapicTimerStop(Mcb);
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MdPitSetCount(MAX_SAMPLES);
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TicksStart = MdPitGetCount();
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LapicRegWrite(Mcb, LAPIC_INIT_CNT, MAX_SAMPLES);
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while (LapicRegRead(Mcb, LAPIC_CUR_CNT) != 0);
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TicksEnd = MdPitGetCount();
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TicksTotal = TicksStart - TicksEnd;
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Freq = (MAX_SAMPLES / TicksTotal) * I8254_DIVIDEND;
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LapicTimerStop(Mcb);
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Mcb->LapicTmrFreq = Freq;
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}
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VOID
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MdLapicSendIpi(UCHAR Vector, UCHAR DestId, BOOLEAN LogicalDest,
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IPI_SHORTHAND Xnd, IPI_DELMOD DelMod)
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{
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KPCR *ThisCore;
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MCB *Mcb;
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ULONG IcrLow, IcrHigh;
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/*
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* If the shorthand is refering to ourselves and we are x2APIC we
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* can use a better path via its specialized SELF IPI MSR.
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*/
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ThisCore = HalKpcrCurrent();
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if (Xnd == IPI_XND_SELF && Mcb->HasX2Apic) {
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MdWrmsr(LAPIC_SELF_IPI, Vector);
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return;
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}
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Mcb = &ThisCore->Mcb;
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IcrLow = 0;
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IcrHigh = 0;
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/* Clamp these fields */
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DelMod &= 7;
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Xnd &= 3;
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/* Encode the ICR */
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IcrLow |= Vector & 0xFF;
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IcrLow |= Xnd << 18;
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IcrLow |= DelMod << 8;
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IcrLow |= LogicalDest << 11;
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/* For xAPIC only */
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if (!Mcb->HasX2Apic) {
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IcrHigh |= (UQUAD)DestId << 24;
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LapicRegWrite(Mcb, LAPIC_ICRHI, IcrHigh);
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LapicRegWrite(Mcb, LAPIC_ICRLO, IcrLow);
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/* Only on legacy xAPICs do we poll */
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for (;;) {
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IcrLow = LapicRegRead(Mcb, LAPIC_ICRLO);
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if (ISSET(IcrLow, IPI_DELSTAT_PENDING))
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HalCpuSpinWait();
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}
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return;
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}
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/* On x2APICs only as it queues */
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LapicRegWrite(Mcb, LAPIC_ICRLO, ((UQUAD)DestId << 32) | IcrLow);
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}
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ULONG
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MdLapicId(VOID)
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{
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KPCR *ThisCore;
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MCB *Mcb;
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ThisCore = HalKpcrCurrent();
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Mcb = &ThisCore->Mcb;
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/* 32-bit when in x2APIC mode */
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if (Mcb->HasX2Apic) {
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return LapicRegRead(Mcb, LAPIC_ID) & 0xFFFFFFFF;
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}
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return (LapicRegRead(Mcb, LAPIC_ID) >> 24) & 0xF;
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}
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VOID
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MdLapicTimerOneshotUs(USIZE Usec)
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{
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UQUAD Ticks;
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KPCR *Kpcr;
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MCB *Mcb;
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Kpcr = HalKpcrCurrent();
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Mcb = &Kpcr->Mcb;
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Ticks = Usec * (Mcb->LapicTmrFreq / 1000000);
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LapicTimerOneShot(Mcb, false, Ticks);
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}
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VOID
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MdLapicSendEoi(VOID)
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{
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KPCR *Kpcr;
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Kpcr = HalKpcrCurrent();
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LapicRegWrite(&Kpcr->Mcb, LAPIC_EOI, 0);
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}
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VOID
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MdLapicInit(KPCR *Kpcr)
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{
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ACPI_MADT *Madt;
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MCB *Mcb;
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if (Kpcr == NULL) {
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KeBugCheck(
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BUGCHECK_MISC,
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"lapic: failed to initialize lapic driver\n"
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);
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}
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if (!LapicIsSupported()) {
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KeBugCheck(
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BUGCHECK_MISSING_HARDWARE,
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"lapic: local apic not supported\n"
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);
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}
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/* Obtain the ACPI MADT table */
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Madt = AcpiQuery("APIC");
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if (Madt == NULL) {
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KeBugCheck(BUGCHECK_MISC, "lapic: could not obtain MADT\n");
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}
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Mcb = &Kpcr->Mcb;
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Mcb->LapicBase = PMA_TO_VMA((UPTR)Madt->LapicAddr);
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Mcb->HasX2Apic = LapicHasX2Apic();
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/* Enable the Local APIC */
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LapicEnable(Mcb);
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/* Calibrate the timer */
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LapicTimerCalibrate(Mcb);
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}
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@@ -0,0 +1,100 @@
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/*
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* Copyright (c) 2026, Chloe M.
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* Provided under the BSD-3 clause.
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*
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* Description: Local APIC driver
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* Author: Chloe M.
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*/
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#ifndef _MACHINE_LAPIC_H_
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#define _MACHINE_LAPIC_H_ 1
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#include <ptdef.h>
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#include <hal/kpcr.h>
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/*
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* Destination shorthand values for inter-processor
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* interrupts.
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*
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* @IPI_XND_NONE: No shorthand
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* @IPI_XND_SELF: Self shorthand
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* @IPI_XND_AIS: All including self shorthand
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* @IPI_XND_AES: All exclduing self shorthand
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*/
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typedef enum {
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IPI_XND_NONE,
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IPI_XND_SELF,
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IPI_XND_AIS,
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IPI_XND_AES
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} IPI_SHORTHAND;
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/*
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* Delivery mode values for inter-processor
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* interrupts.
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*
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* @IPI_DELMOD_FIXED: Deliver a specific interrupt vector to a slutty core~
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* @IPI_LOWPRI: Equivalent to a FIXED IPI but lowest priority
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* @IPI_DELMOD_SMI: Sends an SMI, we don't use this
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* @IPI_DELMOD_RESERVED: Reserved
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* @IPI_DELMOD_NMI: Deliver a non-maskable interrupt
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* @IPI_DELMOD_INIT: Deliver an INIT IPI to a processor
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* @IPI_DELMOD_STARTUP: Deliver a STARTUP IPI to a processor
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*/
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typedef enum {
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IPI_DELMOD_FIXED,
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IPI_DELMOD_LOWPRI,
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IPI_DELMOD_SMI,
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IPI_DELMOD_RESERVED,
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IPI_DELMOD_NMI,
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IPI_DELMOD_INIT,
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IPI_DELMOD_STARTUP
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} IPI_DELMOD;
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/* IPI Delivery status bits */
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#define IPI_DELSTAT_PENDING BIT(12)
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/* IPI Destination mode */
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#define IPI_DELMOD_LOGICAL BIT(0)
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/*
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* Initialize the Local APIC unit for the current
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* processor.
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*
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* @Kpcr: KPCR of current processor
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*/
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VOID MdLapicInit(KPCR *Kpcr);
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/*
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* Obtain the APIC ID of the current processor
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*/
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ULONG MdLapicId(VOID);
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/*
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* Send an inter-processor interrupt
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*
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* @Vector: Interrupt vector to assign to ICR
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* @DestId: Target APIC ID [depends on @LogicalDest]
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* @LogicalDest: If true, IPI destination is logical
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* @Xnd: Destination shorthand
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* @Delmod: Delivery mode
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*/
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VOID MdLapicSendIpi(
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UCHAR Vector, UCHAR DestId,
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BOOLEAN LogicalDest, IPI_SHORTHAND Xnd,
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IPI_DELMOD DelMod
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);
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/*
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* Start the Local APIC timer in oneshot mode and fire after
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* a number of microseconds
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*
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* @Usec: Number of microseconds to fire after
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*/
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VOID MdLapicTimerOneshotUs(USIZE Usec);
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/*
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* Send an end-of-interrupt signal to the Local APIC unit
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*/
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VOID MdLapicSendEoi(VOID);
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#endif /* !_MACHINE_LAPIC_H_ */
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@@ -0,0 +1,27 @@
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/*
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* Copyright (c) 2026, Chloe M.
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* Provided under the BSD-3 clause.
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*
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* Description: Machine core block
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* Author: Chloe M.
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*/
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#ifndef _MACHINE_MCB_H_
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#define _MACHINE_MCB_H_ 1
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#include <ptdef.h>
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/*
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* The machine core block contains MD processor information
|
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*
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* @LapicBase: Local APIC MMIO base
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* @HasX2Apic: Has an x2APIC unit
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* @LapicTmrFreq: Local APIC timer frequency
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*/
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typedef struct {
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VOID *LapicBase;
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UCHAR HasX2Apic : 1;
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USIZE LapicTmrFreq;
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} MCB;
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#endif /* !_MACHINE_MCB_H_ */
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@@ -11,6 +11,7 @@
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#include <ptdef.h>
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#include <ex/pool.h>
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#include <machine/mcb.h>
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||||
|
||||
/*
|
||||
* The kernel processor control region contains MI
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||||
@@ -18,10 +19,12 @@
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*
|
||||
* @Id: Logical processor ID assigned by us
|
||||
* @PoolRegion: Allocator pool region
|
||||
* @Mcb: Machine core block
|
||||
*/
|
||||
typedef struct {
|
||||
USHORT Id;
|
||||
POOL_REGION PoolRegion;
|
||||
MCB Mcb;
|
||||
} KPCR;
|
||||
|
||||
/*
|
||||
|
||||
@@ -87,12 +87,12 @@ KiKernelInit(VOID)
|
||||
/* Initialize virtual memory */
|
||||
MmVmInit();
|
||||
|
||||
/* Phase 2 init of bootstrap core */
|
||||
HalKpcrP2Init(&BootstrapCore);
|
||||
|
||||
/* Initialize ACPI */
|
||||
AcpiInit();
|
||||
|
||||
/* Phase 2 init of bootstrap core */
|
||||
HalKpcrP2Init(&BootstrapCore);
|
||||
|
||||
/* Initialize the root process */
|
||||
InitializeRootProcess();
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user