From 0408b34438c48a268b2196ef11995e33a5a6f987 Mon Sep 17 00:00:00 2001
From: Chloe M <chloe@mensia.org>
Date: Tue, 14 Jul 2026 16:39:22 -0400
Subject: [PATCH] ptos/amd64: cpu: Add Local APIC timer ISR stub

Signed-off-by: Chloe M <chloe@mensia.org>
---
 service/ptos/arch/amd64/cpu/lapic.c  | 8 ++++++++
 service/ptos/arch/amd64/cpu/vector.S | 9 +++++++++
 2 files changed, 17 insertions(+)

diff --git a/service/ptos/arch/amd64/cpu/lapic.c b/service/ptos/arch/amd64/cpu/lapic.c
index 7b45f40..eb1d8c9 100644
--- a/service/ptos/arch/amd64/cpu/lapic.c
+++ b/service/ptos/arch/amd64/cpu/lapic.c
@@ -349,4 +349,12 @@ MdLapicInit(KPCR *Kpcr)
 
     /* Calibrate the timer */
     LapicTimerCalibrate(Mcb);
+
+    /* Set the LAPIC timer ISR gate */
+    MdIdtSetGate(
+        0x81,
+        (UPTR)LapicTmrIsr,
+        IDT_INT_GATE,
+        0
+    );
 }
diff --git a/service/ptos/arch/amd64/cpu/vector.S b/service/ptos/arch/amd64/cpu/vector.S
index ce7957e..aa5efda 100644
--- a/service/ptos/arch/amd64/cpu/vector.S
+++ b/service/ptos/arch/amd64/cpu/vector.S
@@ -143,3 +143,12 @@ TrapPageFault:
 1:  cli
     hlt
     jmp 1b
+
+    .globl LapicTmrIsr
+LapicTmrIsr:
+    INTR_ENTRY($0x81)
+    mov %rsp, %rdi
+    call HalContextSwitch
+1:  cli
+    hlt
+    jmp 1b