ptos/amd64: cpu: Add MP trampoline stub

Signed-off-by: Chloe M <chloe@mensia.org>

service/ptos/arch/amd64/cpu/mp.c

@@ -7,11 +7,18 @@
  */
 
 #include <ptdef.h>
+#include <hal/page.h>
 #include <ex/trace.h>
 #include <drivers/acpi/acpi.h>
 #include <drivers/acpi/tables.h>
 #include <ke/bugcheck.h>
+#include <mm/vm.h>
 #include <machine/lapic.h>
+#include <string.h>
+
+/* Bring up region */
+#define BUA_BASE   0x9000
+#define BUA_LENGTH PAGESIZE
 
 /* Max processors to bootstrap */
 #define CPU_MAX 64
@@ -22,6 +29,13 @@
 /* Number of processor cores */
 static USHORT CoreCount = 0;
 
+/*
+ * The multiprocessor trampoline should fit within a single
+ * page and be no larger than such.
+ */
+ALIGN(8) SECTION(".mp_trampoline")
+static UCHAR MpTrampoline[BUA_LENGTH];
+
 /*
  * Bootstrap a single core
  *
@@ -32,10 +46,18 @@ static USHORT CoreCount = 0;
 static VOID
 BootstrapCore(ACPI_LOCAL_APIC *LocalApic)
 {
+    ULONG SelfId;
+
     if (LocalApic == NULL) {
         return;
     }
 
+    /* Let's not shoot ourselves in the face */
+    SelfId = MdLapicId();
+    if (LocalApic->ApicId == SelfId) {
+        return;
+    }
+
     ++CoreCount;
 }
 
@@ -78,5 +100,34 @@ MpBootstrap(VOID)
 VOID
 HalMpBootstrap(VOID)
 {
+    MMU_VAS Vas;
+    MM_RANGE TrampolineRange;
+    PT_STATUS Status;
+    VOID *BuaDest;
+
+    /* Map the BUA page */
+    HalMmuReadVas(&Vas);
+    TrampolineRange.VirtualBase = BUA_BASE;
+    TrampolineRange.PhysicalBase = BUA_BASE;
+    TrampolineRange.Length = BUA_LENGTH;
+    Status = MmMapRange(
+        &Vas,
+        &TrampolineRange,
+        PAGE_READ | PAGE_WRITE | PAGE_EXEC,
+        PAGESIZE_4K
+    );
+
+    if (PT_ERROR(Status)) {
+        KeBugCheck(
+            BUGCHECK_MISC,
+            "failed to map mp bringup area\n"
+        );
+    }
+
+    /* Copy trampoline to the BUA page */
+    BuaDest = (VOID *)BUA_BASE;
+    RtlMemCpy(BuaDest, MpTrampoline, BUA_LENGTH);
+
+    /* Start up the APs */
     MpBootstrap();
 }