testbench: Add concept source file

Signed-off-by: Ian Moffett <ian@mirocom.org>

1 files changed, 22 insertions, 0 deletions

diff --git a/testbench/concept.cescal b/testbench/concept.cescal
new file mode 100644
index 0000000..6787362
--- /dev/null
+++ b/testbench/concept.cescal
@@ -0,0 +1,22 @@
+//
+// Copyright (c) 2026, Chloe M.
+// Provided under the BSD-3 clause
+//
+
+//
+// Operations can only be performed on registers but not
+// variables. Register names follow this convention:
+// -----------------------------------------------------
+//             r<bitwidth>:name
+//
+pub proc log2(v : u64) -> u64 begin
+    r64:cnt = 0;
+    r64:tmp = v;
+
+    while (r64:tmp != 0) begin
+        r64:tmp >>= 1;
+        r64:cnt += 1;
+    end
+
+    return r64:cnt;
+end